A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit features. To take advantage of increasing number of devices and to form them into one or more circuits, the various devices need to be interconnected.
To accomplish interconnection on such a small scale, a local interconnect is typically used within an integrated circuit to provide an electrical connection between two or more conducting or semi-conducting regions (e.g., active regions of one or more devices). For example, a plurality of transistors can be connected to form an inverting logical circuit using a local interconnect.
The local interconnect is typically a relatively low-resistance material, such as a conductor or doped semiconductor, that is formed to electrically couple the selected regions. For example, in certain arrangements, damascene techniques are used to provide local interconnects made of tungsten (W), or a like conductor, which is deposited within an etched opening, such as a via or trench that connects the selected regions together. The use of local interconnects reduces the coupling burden on the subsequently formed higher layers to provide such connectivity, which reduces the overall circuit size and as such tends to increase the circuit'performance. Accordingly, as the density of the circuits increase there is a continuing need for more efficient, effective and precise processes for forming smaller local interconnects.
With this in mind, FIG. 1 depicts a cross-section of a portion 10 of a prior-art semiconductor wafer having a stop layer 22 and a dielectric layer 26 as prepared for local interconnect processing using conventional deposition processes. As shown, portion 10 includes a substrate 12 in which one or more devices have been formed. By way of example, portion 10 includes a gate 16 that is part of a field effect transistor having a source region 24a and a drain region 24b formed within substrate 12, as is known in the art. Gate 16 is typically a conductive material or a semiconductive material, such as, for example, a doped polycrystalline silicon (referred to hereinafter as polysilicon), which has been formed on a gate oxide 14 (e.g., silicon dioxide SiO.sub.2) on top of substrate 12. A dielectric spacer 20 has been added to each of the vertical sidewalls of gate 16 and the exposed top surface of gate 16 has a conductive silicide 18 formed thereon. Stop layer 22, which is a dielectric material, such as, for example, silicon nitride (e.g., Si.sub.3 N.sub.4), has been deposited over the exposed surfaces of portion 10 using a stop layer deposition process. Dielectric layer 26, such as, for example, tetraethlorthosilicate (TEOS) oxide, has been deposited over stop layer 22 using a conventional deposition process.
Although stop layer 22 and dielectric layer 26 are both dielectric materials, preferably they are different enough in composition such that subsequent etching processes are capable of etching through dielectric layer 26 while essentially stopping on stop layer 22, thereby avoiding the possibility of etching into substrate 12 and the device regions formed therein. In this manner, stop layer 22 tends to provide improved process control in the formation of local interconnects that are formed using damascene techniques.
The continued shrinkage of the critical dimensions of the various components, layers and film, for example in portion 10 of FIG. 1, places new challenges on those seeking to maintain process control. One of these challenges is to maintain control over the dielectric etching process during local interconnect formation, and in particular effectively stopping on stop layer 22.
To help address this problem improved materials and/or etching processes have been developed, and continue to be developed, so as to increase the selectivity of the dielectric etching process to stop layer 22. Unfortunately, these improvements have yet to lead to a process that exhibits perfect selectivity between the dielectric layer 26 and stop layer 22. Consequently, it is possible to over-etch portions of stop layer 22 and "punch-through" to substrate 12 during the dielectric etching process, especially if stop layer 22 is very thin.
This is especially true for high aspect ratio local interconnect trenches/vias that are formed over a non-planar underlying topology. The high aspect ratios (e.g., a ratio of the trench's height to width) and uneven topology of these types of local interconnects usually requires an etching process that is longer in duration so as to effectively etch away dielectric layer 26. For example, if a local interconnect is formed to electrically connect drain region 24b and gate 16, the comer of gate 16 and the curvature of spacer 20 form an uneven topology. Consequently, during the local interconnect etching process, the newly exposed portions of stop layer 22 over the comer of gate 16 and over spacer 18 will be exposed to the etching materials while the remaining areas of dielectric layer 26 are etched away to reveal substrate 12/drain region 24b. In this example, over-etching and/or punch-through occurs if stop layer 22 is breached during the etching of dielectric layer 26 and spacer 18 is etched wholly or partially away as a result. This problem is exacerbated by further dimensional reductions that tend to further reduce the thickness of stop layer 22 and spacer 18 while increasing the aspect ratio of the local interconnect trench/via.
Thus, there is a continuing need for improved methods that increase the process control and prevent over-etching or punch-through during the formation of local interconnects.